In the field of serial data communications, the quality of a serial digital bitstream signal as shown in FIG. 1a is often assessed by observing a visual representation of the amplitude of the signal with respect to time and measuring parameters such as amplitude, pulse width, rise time, fall time, undershoot, overshoot, jitter and distortion. The serial digital bitstream signal has a bit period 120 corresponding to a time period for a single data bit, and an amplitude which can vary between a value (e.g. 0 Volts) corresponding to a logic zero and a value (e.g. 1 Volt) corresponding to a logic 1 (although other signal encodings are possible). The range of amplitudes and the time period corresponding to the bit period 120 define a bit cell 110.
The above parameters of the signal can be assessed from the shape produced by superimposing individual signal traces, each individual signal trace being a single bit period in length, for a plurality of bits of the bitstream signal (as illustrated in FIG. 1b). The shape of the resulting trace broadly resembles the general shape of the human eye: for this reason, traces of this type are often referred to as ‘Eye patterns’. Note: There are other patterns referred to as Eye patterns from their similarity in shape to an eye, in particular patterns deduced from determinations of bit error rates, but the ones discussed in this document are those of the form illustrated in FIG. 1b and mentioned above.
A variety of approaches may be taken to generating Eye Patterns of the form shown in FIG. 1b. Methods disclosed herein use either a very high-speed Analog-to-Digital Converter (ADC) or sample-and-hold Integrated Circuits (sample and hold ICs). An existing circuit for generating Eye Patterns is shown in brief in FIG. 2.
Referring to FIG. 2, a plurality of measurements (or “samples”) 5 of the incoming signal 1 can be taken by the circuit by a sampling module 9. In the circuit of FIG. 2, sampling module 9 always takes each sample 5 of the incoming signal 1 at a nominal sampling position, e.g. at the centre of the bit period 120 (the bit period 120 being determined using the Recovered Clock 2, which clock is recovered using existing means, not shown, from the incoming signal 1). Each of these samples can be referred to as a ‘Data Sample’. Each Data Sample taken by the sampling module 9 can subsequently be processed (not shown) to determine whether the voltage level of the sample is above a selected voltage base level (or “threshold”) in which case the sample is determined to be a “logic one”, or below that threshold in which case the sample is determined to be a “logic zero”.
Some existing circuits also provide the facility, e.g. with sampling module 10 shown in FIG. 2, to record another plurality of measurements (or “samples”) 6 of the incoming signal 1, and to take these other samples using both a ‘vertical’ (amplitude, e.g. voltage) offset 3 and a ‘horizontal’ (time) offset 4 compared with the nominal (or “reference”) data sampling position (e.g. the centre of the bit cell 110). These other samples can be referred to as “Offset Samples”.
FIG. 3 illustrates the centre 11 of a bit cell 110 (which is the position where the Data Samples are taken), and the offset sampling position 12 (where the Offset Samples are taken). The offset sampling position is horizontally offset, i.e. in time, from the nominal sampling position by the horizontal time offset 4, and as shown in FIG. 2 this can be achieved by a module 8 which inserts a time delay into the clock which is used to drive the sampling module 10 which samples the input signal 1 to produce the offset samples 6. Alternatively the input signal 1 can be delayed before being input into the sampling module 10. The offset sampling position is also vertically offset, in amplitude, e.g. in voltage, from the nominal sampling position by the vertical offset 3. As shown in FIG. 2, this can be achieved in practice by for example adding a voltage offset to the input signal 1 before the signal is input to the sampling module 10. Alternatively, instead of adding an offset to the input signal before it is input to sampling module 10, subsequent circuitry which processes the samples 6 can be arranged to apply an offset when processing the samples to determine if each sample is a logic one or a logic zero, e.g. by adding an offset to a voltage reference against which each sample is compared to make the determination.
An Eye Pattern representation of the input signal can be built up by processing multiple samples of the offset sample 6 data obtained using different combinations of horizontal offset and vertical offset which are generated to give full coverage of a range of time delays and a range of voltages, so as to span at least a portion of a bit cell 110. An existing procedure for determining an Eye Pattern Representation of the input signal 1, based on a plurality of offset samples 6, is as follows:
For a plurality of offset data samples taken using a particular vertical offset and a particular horizontal (time) offset, a number (or proportion) of offset samples 6 that are determined to be “logic ones” is recorded. This is repeated using a plurality of different vertical offsets which span the range of voltages of a bit cell 110. The result is a single vertical profile 14, such as that shown in FIG. 4, for the particular horizontal offset, each value along the profile 14 corresponding to a respective number (or proportion) of logic ones for a respective one of the plurality of vertical (voltage) offsets.
The procedure in the above paragraph can then be repeated for a plurality of different horizontal (time) offsets, so as to produce a corresponding plurality of vertical profiles 13,14. The order in which vertical and/or horizontal offsets are sequenced when taking the offset samples of the input signal 1 is not important and can be changed from the above example, e.g. interleaved.
For each of these profiles 13,14, the number/proportion of determined logic ones should be 0 for the highest vertical offset (since for the method to give correct results, the highest vertical offset must be above the highest possible amplitude of the input signal 1), and the number/proportion should be 100% for the lowest vertical offset (which for correct operation needs to be lower than the lowest possible input signal amplitude). Between these two extremes, the measured number/proportion of logic ones provides an indication of the difference between the number of times the signal amplitude is above a particular vertical offset and the number of times that the signal amplitude was below that particular vertical offset.
In accordance with the principles of calculus, the values in each profile 13,14 are then differentiated with respect to their corresponding vertical offsets, to determine an intensity profile which reveals the distribution of input signal amplitudes sampled at that particular horizontal offset (i.e. the relative likelihood of the input signal 1 having a particular amplitude when sampled at the particular horizontal offset within a bit cell 110, or, put another way, the ‘signal intensity’ at that particular vertical and horizontal offset). Data values resulting from this differentiation operation are illustrated in profiles 15 and 16 in FIG. 5 and can be referred to as ‘vertically differentiated slices’.
A plurality of the vertically differentiated slices 15,16 can then be combined side-by-side, to thereby derive an Eye Pattern representation of the input signal 1. For ease of presentation, the different differential data values (corresponding to ‘signal intensity’ at each particular horizontal and vertical offset within a bit period) are typically represented either by a spectrum of colours or by shades of grey, with black used in both cases where the differential is 0 (representing no change in the proportion of ones).
A problem with existing methods of deriving an Eye Pattern representation of an input signal, such as the method described above, is that although the centre of the “eye”, as shown in FIG. 1, should ideally be completely black (i.e. data values of zero), in practice such a circuit as described above tends to generate Eye Patterns which comprise undesirable artefacts (e.g. which appear to be noise and/or errors) in the differential data. Such artefacts are especially noticeable in the centre of the eye, where they typically manifest themselves as “speckling” (e.g. apparently random bright spots) which generally reduces the accuracy with which signal parameters such as rise time, fall time etc. can be determined from the Eye Pattern representation of the signal.